1. Field of the Invention
This invention relates to a semiconductor memory device and a method for producing the memory device. More particularly, it relates to a semiconductor memory device in which a source region and a drain region formed on a substrate of a MOS transistor consist of a high impurity region and a low impurity region, and a method for producing the semiconductor memory device.
2. Description of the Prior Art
As a construction of a MOS transistor in which electrical field concentration in the vicinity of a drain is relaxed to prevent adverse effects of hot carriers, there is known a lightly doped drain structure (LDD structure) in which a high concentration impurity region and a low concentration impurity region are combined together. For producing the LDD structure, the low concentration impurity region is formed in self-alignment with a gate electrode and a sidewall formed by an insulating film is formed on the lateral side of the gate electrode, after which a high concentration impurity region is formed in self-alignment with the sidewall.
In a semiconductor memory device, such as a dynamic RAM, a memory section consisting in a matrix array of a large number of memory cells and a peripheral circuit section for controlling data input and output to or from the memory cell section or signal timing are formed on one and the same substrate.
Meanwhile, with the above semiconductor memory device, the conventional practice has been to produce the MOS transistor of the memory cell section and that of the peripheral circuit section with different LDD structures. The reason is that, in the memory section, in which different layers are densely formed at an extremely small distance from one another, a thicker sidewall is preferred for assuring high voltage withstand characteristics between the gate electrode and other electrodes, whereas, if the sidewall film thickness is larger in the peripheral circuit, the size of the low concentration impurity region accounts for a larger proportion of the size between the source and the drain to increase resistance components or the number of hot carriers to deteriorate the current driving capability of the peripheral circuit in driving the MOS transistor.
Consequently, in some of the conventional semiconductor memory devices, the memory section has a sidewall having a larger sidewall thickness, whereas the peripheral circuit has a sidewall having a smaller sidewall thickness, such that the memory cell and peripheral circuit sections have different LDD structures.
This type of the semiconductor memory device is fabricated by a process shown in FIGS. 1 to 4.
The conventional method for producing the semiconductor memory device is explained by referring to FIGS. 1 to 4.
In a first step, shown in FIG. 1, a gate electrode 102 on the side of a memory cell section M and a gate electrode 103 on the side of a peripheral circuit section P are deposited on a silicon substrate 101 via gate oxide films. An interlayer insulating film for offsetting 104 is also deposited on the gate electrode 102 of the memory cell section M. A low concentration impurity region 105 is deposited on the substrate surface in self-alignment with the gate electrodes 102, 103. After deposition of the low concentration impurity region 105, a silicon oxide film 106, a silicon nitride film 107 and a silicon oxide film 108 are deposited step by step on the entire surface for forming a sidewall.
Then, as shown in FIG. 2, etching is carried out, using a resist layer 113, opened only at the side of the peripheral circuit P, as a mask. By this etching, the silicon oxide film 108 on the silicon nitride film 107 is etched by wet etching, and subsequently the silicon oxide film 106 is etched by reactive ion etching (RIE), as a result of which a sidewall 109 having a reduced film thickness dp corresponding to the film thickness of only the silicon oxide film 106 is formed on the sidewall of the gate electrode 103.
Then, as shown in FIG. 3, the memory cell section M is etched, using a resist layer 110 covering the peripheral circuit section P as a mask. Since the silicon oxide film 106, silicon nitride film 107 and the silicon oxide film 108 are etched by this etching by RIE, a sidewall 111 having an increased film thickness dm is formed on the lateral sides of the gate electrode 102 and the interlayer insulating film 104.
After the sidewalls 109, 111 having different film thicknesses for the peripheral circuit section P and the memory cell section M are formed in this manner, a high concentration impurity region 112 is deposited by ion implantation, using the sidewalls 109, 111, gate electrodes 102, 103 and a field oxide film, not shown, as a mask. Since the sidewalls 109, 111 have different film thicknesses, the high concentration impurity region 112 is different in size at a side adjacent to the sidewall 109 and at a side adjacent to the sidewall 111, such that the size of the low concentration impurity region 105 at the bottom of the sidewall becomes shorter at the side of the peripheral circuit section P.
However, if the semiconductor memory device is to be produced by the above-described method, the peripheral circuit section P and the memory cell section M are alternately covered with the resist layers 110, 113. Since a margin is set in the resist layers 110, 113 to take account of masking errors, the resist layers 110, 113 are overlapped with each other at a boundary between the peripheral circuit section P and the memory cell section M, as a result of which the silicon oxide films 106, 108 and the silicon nitride film 107 are left in the form of a pattern.
In addition, the lithographic process needs to be carried out twice with the above method for sidewall formation, while the peripheral circuit section P needs to be etched by wet etching, thus complicating the production process.